bridge_gic_sprt_10_100_btrl_2 

         This register holds a unique 8-bit identifier for the transmitting bridge. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element.
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF7014090

Size: 32

Offset: 0x14090

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UNSD_31_21

RO 0x0

EN

RW 0x0

CNT

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WT

RW 0x0

bridge_gic_sprt_10_100_btrl_2 Fields

Bit Name Description Access Reset
31:21 UNSD_31_21
RO 0x0
20 EN 
                 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only
RW 0x0
19:16 CNT 
                 -: Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC
RW 0x0
15:0 WT 
                 -: Starting Weight, for traffic issue to the NoC from the host interface
RW 0x0