bridge_ram_sprt_14_80_brus

         This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. This is a read-only register.

Module Instance	Base Address	Register Address
`i_ccu_noc_registers`	`0xF7000000`	`0xF70241B0`

Size: 32

Offset: 0x241B0

Access: RO

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`UNSD_31_4` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`

bridge_ram_sprt_14_80_brus Fields

Bit	Name	Description	Access	Reset
31:4	`UNSD_31_4`		`RO`	`0x0`
3	`VALID_IF_D`	-: Interface D upsizer/downsizer valid	`RO`	`0x0`
2	`VALID_IF_C`	-: Interface C upsizer/downsizer valid	`RO`	`0x0`
1	`VALID_IF_B`	-: Interface B upsizer/downsizer valid	`RO`	`0x0`
0	`VALID_IF_A`	-: Interface A upsizer/downsizer valid	`RO`	`0x0`