bridge_tcu_mprt_3_70_am_admask_mem_ram_sprt_ramspace2_0 

         These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above  base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation
 AxADDRS & AM_ADMASK[i] == AM_ADBASE[i]
 Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed  base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of  these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt.
 Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF702C628

Size: 64

Offset: 0x2C628

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

MASK

RW 0x3FFFFFF800

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

MASK

RW 0x3FFFFFF800

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MASK

RW 0x3FFFFFF800

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MASK

RW 0x3FFFFFF800

RSV

RW 0x0

VALID

RW 0x0

I

RW 0x0

NS

RW 0x0

P

RW 0x0

bridge_tcu_mprt_3_70_am_admask_mem_ram_sprt_ramspace2_0 Fields

Bit Name Description Access Reset
63:6 MASK 
                 -: Mask
RW 0x3FFFFFF800
5:4 RSV 
                 -: Reserved
RW 0x0
3 VALID 
                 1'b1: R_Wn field is valid
RW 0x0
2 I 
                 1'b1: Instruction field is valid
RW 0x0
1 NS 
                 1'b1: Non-secure field is valid
RW 0x0
0 P 
                 1'b1: Privileged field is valid
RW 0x0