agent_ccc0_ccc_indirect_access_trig 

         This registers is the indirect access trigger. Indirect access is a mechanism that allows register-based access to the directory RAM. This can be used for testing RAM bits or reading content on an error condition.
The indirect access is based on a content+trigger mechanism. For writes, the content register is written first to accumulate the data that should be written. Once the content is ready, the trigger register is used to kick off the hardware write mechanism. For reads, the trigger register kicks off a read, and provides data by placing the result into the content registers where it can be accessed.
Each of the indirect access commands can be issued during normal operation, but the Write commands can have side-effects that break coherency functionality. The Read Raw is not disruptive, and the Read-Modify-Write can be performed atomically so single-bit errors can be introduced while maintaining functionality.
The indirect access trigger registers is readable and writeable. To trigger the RAM access, this register must be written. Reads will not have side-effects and 
will only return the current value of the trigger register.
The trigger register has a number of fields that must be set correctly. The CMD field indicates which kind of indirect access to perform. The WAY field indicates 
whether RAM 0 or 1 should be accessed. The RAM index indicates the entry to access within the RAM. The RAM index is a pure index, which will avoid any hashing function for WAY 1.
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF7030088

Size: 64

Offset: 0x30088

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

UNSD

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

UNSD

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UNSD

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UNSD

RO 0x0

INDEX

RW 0x0

WAY

RW 0x0

CMD

RW 0x0

agent_ccc0_ccc_indirect_access_trig Fields

Bit Name Description Access Reset
63:15 UNSD 
                 -: Unused
RO 0x0
14:3 INDEX
RW 0x0
2 WAY
RW 0x0
1:0 CMD 
                 11: Read Raw data. When triggered, a read to the directory RAM will be performed and the resulting data, without ECC correction, will be copied into the content register.
10: Write Raw Data. When triggered, the content register values will be written into the directory RAM. This will include the ECC bits if present.
01:  Write Data with Generated ECC. When triggered, this will write to the RAM entry. The content register will be used to specify the data to be written. However, if ECC hardware is present, the ECC bits will be generated based on the data instead of coming from the content register. This allows a directory entry to be written with correct ECC value without needing to calculate it first.
00: Read-Modify-Write. This command will perform a specific kind of read-modify-write operation on a directory entry. It will read the content of the directory, XOR that content with the indirect content register, and write the combined value into the same directory entry. This can be used to introduce single or double bit errors into the directory to test error detection and handling. The content register will not be modified during this operation, so it can be used to introduce errors into multiple lines.
RW 0x0