agent_ccc0_ccc_spec_fetch_2

         This register controls the speculative fetch behavior of the Cache Coherency Controller. Speculative fetch means that the CCC will issue reads to memory or next level of cache before the directory lookup is performed or the snoops are sent.  This allows a lower latency  for these reads in the case of a directory miss.  If snoops need to be sent for this request, data may be retrieved from a caching agent.  This means the speculative fetch may be increasing memory bandwidth in case where it wouldn't have needed to send a read.
This set of registers specifies a bit vector where each bit corresponds to a master agent on the NoC.  When requests from this agent arrive at the CCC, a comparison with the bit vector will determine whether speculative fetch is currently enabled for that agent.
The bit vector is sized based on the number of masters in the system.  The bit position of each agent is determined by the agent's bridge ID. Unused bits are not included in the register and cannot be written.
A value of 1 means speculative fetch is enabled for that agent. A value of 0 means speculative fetch is disabled for that agent. The initial values are determined by the bridge property cc_axi4m_speculative_fetch.

Module Instance	Base Address	Register Address
`i_ccu_noc_registers`	`0xF7000000`	`0xF7030010`

Size: 64

Offset: 0x30010

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`SPEC_FETCH_VECTOR` `RW 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`SPEC_FETCH_VECTOR` `RW 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`SPEC_FETCH_VECTOR` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`SPEC_FETCH_VECTOR` `RW 0x0`

agent_ccc0_ccc_spec_fetch_2 Fields

Bit	Name	Description	Access	Reset
63:0	`SPEC_FETCH_VECTOR`	-: Speculative fetch vector	`RW`	`0x0`