bridge_tcu_mprt_3_70_am_sts 

         When reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet.
When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF702FD00

Size: 64

Offset: 0x2FD00

Access: RO

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

UNSD_63_8

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

UNSD_63_8

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UNSD_63_8

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UNSD_63_8

RO 0x0

AWO

RO 0x0

ARO

RO 0x0

AWS

RO 0x0

ARS

RO 0x0

WOE

RO 0x1

ROE

RO 0x1

WOF

RO 0x0

ROF

RO 0x0

bridge_tcu_mprt_3_70_am_sts Fields

Bit Name Description Access Reset
63:8 UNSD_63_8
RO 0x0
7 AWO 
                 1'b1: Write commands are outstanding to the slave specified in OSSLV register
RO 0x0
6 ARO 
                 1'b1: Read commands are outstanding to the slave specified in OSSLV register
RO 0x0
5 AWS 
                 1'b1: AW channel is stalled on hazard
RO 0x0
4 ARS 
                 1'b1: AR channel is stalled on hazard
RO 0x0
3 WOE
RO 0x1
2 ROE
RO 0x1
1 WOF 
                 1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted
1'b0: Master bridge can accept more write requests
RO 0x0
0 ROF 
                 1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted
1'b0: Master bridge can accept more read requests
RO 0x0