bridge_ddrreg_sprt_8_118_p_0 

         This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of priority and weight, however only the weight is programmable, therefore is part of the registers.
QoS data is composed of four registers, P0, P1, P2, and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF7008000

Size: 32

Offset: 0x8000

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WT_QOS_3

RW 0x3

WT_QOS_2

RW 0x3

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WT_QOS_1

RW 0x3

WT_QOS_0

RW 0x3

bridge_ddrreg_sprt_8_118_p_0 Fields

Bit Name Description Access Reset
31:24 WT_QOS_3 
                 -: Weight of QoS profile 3
RW 0x3
23:16 WT_QOS_2 
                 -: Weight of QoS profile 2
RW 0x3
15:8 WT_QOS_1 
                 -: Weight of QoS profile 1
RW 0x3
7:0 WT_QOS_0 
                 -: Weight of QoS profile 0
RW 0x3