agent_ccc0_ccc_interrupt_mask 

         This register is used for determining what kind of events can trigger an interrupt from the CCC. A bit value of 1 indicates that the event will not send an interrupt. A bit value of 0 means the event will cause an interrupt. The default value is 3'b110, which means only the Multi-bit error case will send an interrupt, as it is a fatal error.
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF7030190

Size: 64

Offset: 0x30190

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

UNSD_63_3

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

UNSD_63_3

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UNSD_63_3

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UNSD_63_3

RO 0x0

M2

RW 0x1

M1

RW 0x1

M0

RW 0x0

agent_ccc0_ccc_interrupt_mask Fields

Bit Name Description Access Reset
63:3 UNSD_63_3
RO 0x0
2 M2 
                 1'b1: Event counter overflow interrupt enable
RW 0x1
1 M1 
                 1'b1: Single-bit error interrupt enable
RW 0x1
0 M0 
                 1'b1: Multi-bit error interrupt enable
RW 0x0