bridge_tcu_mprt_3_70_am_err 

         These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. e0 - e7 are relative to AR channel. e16 - e23 are WR channel counter parts.
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF702FE00

Size: 64

Offset: 0x2FE00

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

UNSD_63_41

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

UNSD_63_41

RO 0x0

E40

RW 0x0

UNSD_39_35

RO 0x0

E34

RW 0x0

E33

RW 0x0

E32

RW 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UNSD_31_25

RO 0x0

E24

RW 0x0

E23

RW 0x0

E22

RW 0x0

E21

RW 0x0

E20

RW 0x0

E19

RW 0x0

E18

RW 0x0

E17

RW 0x0

E16

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UNSD_15_9

RO 0x0

E8

RW 0x0

E7

RW 0x0

E6

RW 0x0

E5

RW 0x0

E4

RW 0x0

E3

RW 0x0

E2

RW 0x0

E1

RW 0x0

E0

RW 0x0

bridge_tcu_mprt_3_70_am_err Fields

Bit Name Description Access Reset
63:41 UNSD_63_41
RO 0x0
40 E40 
                 1'b1: Indicates that portcheck detected error (SIB mode only)
RW 0x0
39:35 UNSD_39_35
RO 0x0
34 E34 
                 1'b1: Traffic sent to a noc layer which is power gate
RW 0x0
33 E33 
                 1'b1: Capture counter1 overflow
RW 0x0
32 E32 
                 1'b1: Capture counter0 overflow
RW 0x0
31:25 UNSD_31_25
RO 0x0
24 E24 
                 1'b1: Unexpected narrow write detected
RW 0x0
23 E23 
                 1'b1: Write WRAP not equal to supported cacheline size
RW 0x0
22 E22 
                 1'b1: Write respone timeout
RW 0x0
21 E21 
                 1'b1: Write address multi-hit
RW 0x0
20 E20 
                 1'b1: Write exclusive split
RW 0x0
19 E19 
                 1'b1: Non modifiable WRAP
RW 0x0
18 E18 
                 1'b1: Write slave error
RW 0x0
17 E17 
                 1'b1: Write address decode error from slave
RW 0x0
16 E16 
                 1'b1: Local write address decode error
RW 0x0
15:9 UNSD_15_9
RO 0x0
8 E8 
                 1'b1: Unexpected narrow read detected
RW 0x0
7 E7 
                 1'b1: Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected
RW 0x0
6 E6 
                 1'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval
RW 0x0
5 E5 
                 1'b1: Read address multi-hit: An AR command matched against multiple entries in the address table
RW 0x0
4 E4 
                 1'b1: Read exclusive split: An AR command of FIXED burst type was detected
RW 0x0
3 E3 
                 1'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected
RW 0x0
2 E2 
                 1'b1: Read slave error: A slave error response was received from a slave device
RW 0x0
1 E1 
                 1'b1: Read address decode error from slave: A decode error response was received from a slave device
RW 0x0
0 E0 
                 1'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued
RW 0x0