bridge_rbm_m_16_66_brs_5

         These registers track the status of the bridge's receive FIFOs from the NoC. Since there is up to 16 layers of the NoC, there are 16 registers. Each register tracks the status of one virtual channel, with up to 4 virtual channels per layer. This is a read-only register.

Module Instance	Base Address	Register Address
`i_ccu_noc_registers`	`0xF7000000`	`0xF7000158`

Size: 32

Offset: 0x158

Access: RO

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`

bridge_rbm_m_16_66_brs_5 Fields

Bit	Name	Description	Access	Reset
31:30	`UNSD_31_30`		`RO`	`0x0`
29	`F_3`	-: Buffer full for VC 5	`RO`	`0x0`
28	`B_3`	-: Head flit barrier state for VC 5	`RO`	`0x0`
27	`S_3`	-: Head flit sop5	`RO`	`0x0`
26	`V_3`	-: Head flit (buffer ready)5	`RO`	`0x0`
25:24	`OUTI_3`	-: Head flit output interface	`RO`	`0x0`
23:22	`UNSD_23_22`		`RO`	`0x0`
21	`F_2`	-: Buffer full for VC 5	`RO`	`0x0`
20	`B_2`	-: Head flit barrier state for VC 5	`RO`	`0x0`
19	`S_2`	-: Head flit sop5	`RO`	`0x0`
18	`V_2`	-: Head flit (buffer ready)5	`RO`	`0x0`
17:16	`OUTI_2`	-: Head flit output interface	`RO`	`0x0`
15:14	`UNSD_15_14`		`RO`	`0x0`
13	`F_1`	-: Buffer full for VC 5	`RO`	`0x0`
12	`B_1`	-: Head flit barrier state for VC 5	`RO`	`0x0`
11	`S_1`	-: Head flit sop5	`RO`	`0x0`
10	`V_1`	-: Head flit (buffer ready)5	`RO`	`0x0`
9:8	`OUTI_1`	-: Head flit output interface	`RO`	`0x0`
7:6	`UNSD_7_6`		`RO`	`0x0`
5	`F_0`	-: Buffer full for VC 5	`RO`	`0x0`
4	`B_0`	-: Head flit barrier state for VC 5	`RO`	`0x0`
3	`S_0`	-: Head flit sop5	`RO`	`0x0`
2	`V_0`	-: Head flit (buffer ready)5	`RO`	`0x0`
1:0	`OUTI_0`	-: Head flit output interface	`RO`	`0x0`