agent_ccc0_ccc_directory_inv 

         This is a control register that can be used to invalidate the entire directory. Setting this register will kick off a hardware engine that will block normal coherent traffic and invalidate all entries of the directory.
The register also acts as a status register. When the control bit is set, it triggers the hardware state machine. The value of that register will stay high 
until the state machine completes. At that point, it will automatically transition to 0. Since coherent traffic will be blocked until the invalidation sequence 
has completed, it is not always necessary to check the status of this register.
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF7030080

Size: 64

Offset: 0x30080

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

ZERO

RW 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

ZERO

RW 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ZERO

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ZERO

RW 0x0

VLD

RW 0x0

agent_ccc0_ccc_directory_inv Fields

Bit Name Description Access Reset
63:1 ZERO 
                 -: Zeroes
RW 0x0
0 VLD 
                 1'b1: Writing a value of 1 will trigger the invalidation engine, and it will transition to 0 when completed
RW 0x0