agent_dvm0_dvm_active_vector_0

         ACTIVE_VECTOR_0/1/2/3: Register indicating active DVM agents in the system.
The DVM IP module is parameterized for a maximum number of agents supporting DVM in the system. This parameterization is taken care of by NocStudio. When reset is de-asserted, the DVM IP module expects that all specified DVM agents in the system are active. This is reflected in this readable, 
writable ACTIVE_VECTOR register. If, due to low power mode, or other reasons, a DVM agent in the system is shut down, the DVM IP module needs to be made aware of this. To do this, the bit position of the DVM agent in this ACTIVE_VECTOR register should be set to 0.
On seeing a 0 for an agent in the ACTIVE_VECTOR, the DVM IP module ensures that no snoops are sent to it, and does not wait for snoop responses or completions from this agent.
The maximum number of DVM agents supported is 256. The entire vector can hence take from one to four 64-bit registers. Unused bits within the 64-bit registers are tied to 0.
Each agent, or host, in the system is assigned a corresponding bridge ID, based on the bridge it is connected to. The active vector register is based on this bridge ID.
ACTIVE_VECTOR_0 contains the vector for agents with bridge ID 0 to 63.
ACTIVE_VECTOR_1 contains the vector for agents with bridge ID 64 to 127.
ACTIVE_VECTOR_2 contains the vector for agents with bridge ID 128 to 191.
ACTIVE_VECTOR_3 contains the vector for agents with bridge ID 192 to 255.
For example, if the host at bridge ID=2 is being shut down, bit 2 of ACTIVE_VECTOR_0 should be set to 0. If the host at bridge ID=68 is being shut down, bit 4 of ACTIVE_VECTOR_1 should be set to 0.

Module Instance	Base Address	Register Address
`i_ccu_noc_registers`	`0xF7000000`	`0xF7034000`

Size: 64

Offset: 0x34000

Access: RO

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`ACTIVE_VECTOR` `RO 0xB`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`ACTIVE_VECTOR` `RO 0xB`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`ACTIVE_VECTOR` `RO 0xB`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ACTIVE_VECTOR` `RO 0xB`

agent_dvm0_dvm_active_vector_0 Fields

Bit	Name	Description	Access	Reset
63:0	`ACTIVE_VECTOR`	-: Active vector	`RO`	`0xB`