bridge_mem0_sprt_13_118_rxid
This register holds a unique 8-bit identifier for the receiving bridge. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_ccu_noc_registers | 0xF7000000 | 0xF70201B8 |
Size: 32
Offset: 0x201B8
Access: RO
Access mode: SECURE | PRIVILEGEMODE
Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
UNSD_31_16 RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ZEROES RO 0x0 |
ID RO 0xD |
||||||||||||||
bridge_mem0_sprt_13_118_rxid Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:16 | UNSD_31_16 |
|
RO | 0x0 |
| 15:8 | ZEROES |
-: Forced to zero
|
RO | 0x0 |
| 7:0 | ID |
-: A unique 8-bit identifier assigned to the bridge to uniquely identify it on the NoC. It is equal to the corresponding TXID 8-bit identifier on the Tx side of the bridge.
|
RO | 0xD |