bridge_cpu0_mprt_0_37_am_intm 

         Interrupt mask register. Individual bit positions match the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF7007E40

Size: 64

Offset: 0x7E40

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

UNSD_63_41

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

UNSD_63_41

RO 0x0

M40

RW 0x0

UNSD_39_35

RO 0x0

M34

RW 0x1

M33

RW 0x1

M32

RW 0x1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UNSD_31_25

RO 0x0

M24

RW 0x0

M23

RW 0x0

M22

RW 0x1

M21

RW 0x0

M20

RW 0x0

M19

RW 0x1

M18

RW 0x1

M17

RW 0x1

M16

RW 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UNSD_15_9

RO 0x0

M8

RW 0x0

M7

RW 0x0

M6

RW 0x1

M5

RW 0x0

M4

RW 0x0

M3

RW 0x1

M2

RW 0x1

M1

RW 0x1

M0

RW 0x1

bridge_cpu0_mprt_0_37_am_intm Fields

Bit Name Description Access Reset
63:41 UNSD_63_41
RO 0x0
40 M40 
                 1'b1: Mask interrupt for SIB portcheck error (SIB mode only)
RW 0x0
39:35 UNSD_39_35
RO 0x0
34 M34 
                 1'b1: Mask interrupt on traffic to PG layer
RW 0x1
33 M33 
                 1'b1: Counter 1 overflow interrupt mask
RW 0x1
32 M32 
                 1'b1: Counter 0 overflow interrupt mask
RW 0x1
31:25 UNSD_31_25
RO 0x0
24 M24 
                 1'b1: Mask interrupt for write channel
RW 0x0
23 M23 
                 1'b1: Mask interrupt for write channel
RW 0x0
22 M22 
                 1'b1: Mask interrupt for write channel
RW 0x1
21 M21 
                 1'b1: Mask interrupt for write channel
RW 0x0
20 M20 
                 1'b1: Mask interrupt for write channel
RW 0x0
19 M19 
                 1'b1: Mask interrupt for write channel
RW 0x1
18 M18 
                 1'b1: Mask interrupt for write channel
RW 0x1
17 M17 
                 1'b1: Mask interrupt for write channel
RW 0x1
16 M16 
                 1'b1: Mask interrupt for write channel
RW 0x1
15:9 UNSD_15_9
RO 0x0
8 M8 
                 1'b1: Mask interrupt for read channel
RW 0x0
7 M7 
                 1'b1: Mask interrupt for read channel
RW 0x0
6 M6 
                 1'b1: Mask interrupt for read channel
RW 0x1
5 M5 
                 1'b1: Mask interrupt for read channel
RW 0x0
4 M4 
                 1'b1: Mask interrupt for read channel
RW 0x0
3 M3 
                 1'b1: Mask interrupt for read channel
RW 0x1
2 M2 
                 1'b1: Mask interrupt for read channel
RW 0x1
1 M1 
                 1'b1: Mask interrupt for read channel
RW 0x1
0 M0 
                 1'b1: Mask interrupt for read channel
RW 0x1