bridge_ram_sprt_14_80_as_sts 

         Slave bridge status bits.
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF7025D00

Size: 64

Offset: 0x25D00

Access: RO

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

UNSD_63_4

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

UNSD_63_4

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UNSD_63_4

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UNSD_63_4

RO 0x0

ROE

RO 0x1

WOE

RO 0x1

ROF

RO 0x0

WOF

RO 0x0

bridge_ram_sprt_14_80_as_sts Fields

Bit Name Description Access Reset
63:4 UNSD_63_4
RO 0x0
3 ROE 
                 1'b1: There are no read commands outstanding to the attached slave device
RO 0x1
2 WOE 
                 1'b1: There are no write commands outstanding to the attached slave device
RO 0x1
1 ROF 
                 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received.
1'b0: Slave bridge can accept more read commands from the NoC
RO 0x0
0 WOF 
                 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received.
1'b0: Slave device can expect more write commands from NoC
RO 0x0