agent_dvm0_dvm_sts

         This register indicates the 'busy' or non-idle state of the internal logic within the DVM IP module. When all traffic has been serviced, and no new transactions are received, the bitwise-AND of these bits will be 0, indicating a state of quiescence.

Module Instance	Base Address	Register Address
`i_ccu_noc_registers`	`0xF7000000`	`0xF7034040`

Size: 64

Offset: 0x34040

Access: RO

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`UNSD_63_13` `RO 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`UNSD_63_13` `RO 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`UNSD_63_13` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`UNSD_63_13` `RO 0x0`			`A` `RO 0x0`	`O` `RO 0x0`	`C` `RO 0x0`	`S` `RO 0x0`	`D7` `RO 0x0`	`D6` `RO 0x0`	`D5` `RO 0x0`	`D4` `RO 0x0`	`D3` `RO 0x0`	`D2` `RO 0x0`	`D1` `RO 0x0`	`D0` `RO 0x0`	`F` `RO 0x0`

agent_dvm0_dvm_sts Fields

Bit	Name	Description	Access	Reset
63:13	`UNSD_63_13`		`RO`	`0x0`
12	`A`	1'b1: Snoop arbiter not idle	`RO`	`0x0`
11	`O`	1'b1: Sync tracker returning sync response to originating agent	`RO`	`0x0`
10	`C`	1'b1: Sync tracker waiting for completions	`RO`	`0x0`
9	`S`	1'b1: Sync tracker sending snoops	`RO`	`0x0`
8	`D7`	1'b1: DRT entry 7 not empty	`RO`	`0x0`
7	`D6`	1'b1: DRT entry 6 not empty	`RO`	`0x0`
6	`D5`	1'b1: DRT entry 5 not empty	`RO`	`0x0`
5	`D4`	1'b1: DRT entry 4 not empty	`RO`	`0x0`
4	`D3`	1'b1: DRT entry 3 not empty	`RO`	`0x0`
3	`D2`	1'b1: DRT entry 2 not empty	`RO`	`0x0`
2	`D1`	1'b1: DRT entry 1 not empty	`RO`	`0x0`
1	`D0`	1'b1: DRT entry 0 not empty	`RO`	`0x0`
0	`F`	1'b1: Input FIFO not empty	`RO`	`0x0`