agent_ccc0_ccc_indirect_ram_cont_5

         This is the indirect access RAM content register. Its use is conjunction with the indirect access trigger register. On an indirect read, data is written to this register. On an indirect write, content from this register is written into the RAM. On a read-modify-write, content from this register is used for the XOR function.
Since the RAM data width may be larger than 64 bits, multiple registers are used to hold the data. Any bits beyond the data width are unused.
      
Module Instance Base Address Register Address
i_ccu_noc_registers 0xF7000000 0xF70300B8

Size: 64

Offset: 0x300B8

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RAM_CONTENTS_383_320

RW 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RAM_CONTENTS_383_320

RW 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RAM_CONTENTS_383_320

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RAM_CONTENTS_383_320

RW 0x0

agent_ccc0_ccc_indirect_ram_cont_5 Fields

Bit Name Description Access Reset
63:0 RAM_CONTENTS_383_320
                 
                 
RW 0x0