Visible to Intel only — GUID: xdl1704169125516
Ixiasoft
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
Visible to Intel only — GUID: xdl1704169125516
Ixiasoft
6. Interfaces and Signal Descriptions
Figure 14. Low Latency 40G Ethernet Intel® FPGA IP Signals and Interfaces Block Diagram
Section Content
TX MAC Interface to User Logic
RX MAC Interface to User Logic
GTS Transceivers Signals
GTS Transceiver Reconfiguration Signals
Avalon Memory-Mapped Management Interface
Miscellaneous Status and Debug Signals
Reset Signals
Clocks
Flow Control Interface
GTS Reset Sequencer Intel FPGA IP