Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813652
Date 7/22/2024
Public
Document Table of Contents

9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

Date Quartus® Prime Version IP version Changes
2024.07.22 24.2 3.0.0
  • Added note indicating that the IP does not support speed grade of '6' in Table: Slowest Supported Device Speed Grades.
  • Updated the release information in Table: Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) for Current Release Information.
  • Added analog parameter section in Low Latency 40G Ethernet Intel® FPGA IP Parameters.
  • Updated the following parameters in Table: Low Latency 40G Ethernet Intel® FPGA IP Parameters: Main Tab:
    • Added Enable cdr dedicated clk option
    • Added 312.5 MHz and 322.265625 MHz as PHY reference frequencies
  • Added IPUpgardeLog.xml in Table: IP Generated Files.
  • Added cdr_divclk signals in Table: Transceiver Signals.
  • Added reconfig_readdatavalid signals in Table: Transceiver Reconfiguration Signals.
  • Updated the following figures:
    • Clocks
    • Reset Sequence
    • Low Latency 40G Ethernet Intel® FPGA IP Signals and Interfaces Block Diagram
2024.04.01 24.1 2.1.0 Initial release.