Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 7/22/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX MAC Datapath 4.4. RX MAC Datapath 4.5. Flow Control 4.6. Frame Status Checking 4.7. Link Fault Signaling Interface
4.3. TX MAC Datapath x
4.3.1. Preamble Pass-through/Insertion 4.3.2. Padding Bytes Insertion 4.3.3. Deficit Idle Count 4.3.4. TX CRC Insertion/Passthrough 4.3.5. TX Avalon® Streaming Filter 4.3.6. TX PCS 4.3.7. PMA
4.4. RX MAC Datapath x
4.4.1. RX Preamble Pass-through or Removal 4.4.2. RX CRC Checking and Dynamic Option to Forward 4.4.3. Strict SFD/Preamble Checking 4.4.4. RX PCS Functional Description
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
4.6. Frame Status Checking x
4.6.1. Frame Type Checking 4.6.2. Length Checking
5. Clocking and Reset Requirements x
5.1. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. GTS Transceivers Signals 6.4. GTS Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface 6.10. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

6.3. GTS Transceivers Signals

The GTS Transceiver PHY IP uses four GTS PMA transceivers for the Low Latency 40G Ethernet Intel® FPGA IP. For more information, refer to the GTS Transceiver PHY User Guide .

The transceivers require a PLL ref clk as an input. The GTS PMA transceiver is configured for a specific setting in order for the successful integration of the existing Low Latency 40G Ethernet MAC and PCS with the GTS PMA transceiver.

Clock Mode – Non-External clock mode.

tx_clkout [0] of the GTS PMA transceiver is connected to tx_coreclkin [0],[1],[2],[3].

rx_clkout [0] of the GTS PMA transceiver is connected to rx_coreclkin [0],[1],[2],[3].

Pll_reference of GTS PMA transceiver is configured to be 156.25 MHz. This also works with 312.5 MHz, however the GTS PMA transceiver must be configured again for the same.

The tx_clkout and rx_clkout is configured to be half-rate, which is 161.13 MHz.

There are two PLLs that convert the 161.13 MHz to 312.5 MHz.

The TX PLL reference clock input is tx_clkout[0], whereas the RX PLL reference clock input is rx_clkout[0].

For SYNC-E, the recovered clock that is rx_clkout[1] from GTS PMA transceiver is used. This is of frequency 312.5 MHz.

Table 18.  GTS Transceiver Signals

Signal

Direction

Width

Description

tx_serial Output 4 TX transceiver data. Each tx_serial bit becomes two physical pins that form a differential pair.
rx_serial Input 4 RX transceiver data. Each rx_serial bit becomes two physical pins that form a differential pair.
clk_ref_p Input 1 The PLL reference clock used by TX and RX. Input to the clock data recovery (CDR) circuitry in the RX PMA.
cdr_divclk Output 1 Dedicated RX recover divided clock output from PMA over the local reference clocks pins or dedicated CDR clock output pins. This clock is available only if you turn on “Enable SyncE” and enable cdr clkout in the IP parameter editor. The normal frequency of cdr_divclk is the input PMA ref clockenb (clk_ref_p/n) divided by 4.

The cdr_divclk uses the clk_ref pin for routing. When cdr_divclk is enabled, the number of available ref clocks is reduced to one except in Agilex™ 5 devices.

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