Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813652
Date 7/22/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX MAC Datapath 4.4. RX MAC Datapath 4.5. Flow Control 4.6. Frame Status Checking 4.7. Link Fault Signaling Interface
4.3. TX MAC Datapath x
4.3.1. Preamble Pass-through/Insertion 4.3.2. Padding Bytes Insertion 4.3.3. Deficit Idle Count 4.3.4. TX CRC Insertion/Passthrough 4.3.5. TX Avalon® Streaming Filter 4.3.6. TX PCS 4.3.7. PMA
4.4. RX MAC Datapath x
4.4.1. RX Preamble Pass-through or Removal 4.4.2. RX CRC Checking and Dynamic Option to Forward 4.4.3. Strict SFD/Preamble Checking 4.4.4. RX PCS Functional Description
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
4.6. Frame Status Checking x
4.6.1. Frame Type Checking 4.6.2. Length Checking
5. Clocking and Reset Requirements x
5.1. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. GTS Transceivers Signals 6.4. GTS Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface 6.10. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

6.2. RX MAC Interface to User Logic

The RX MAC provides an Avalon® streaming interface to the FPGA fabric. The datapath comprises 2, 64-bit words. A valid FCS for a packet results in l2_rx_error bit 1 being low when l2_rx_endofpacket is high. An FCS violation is indicated when l2_rx_error bit 1 is high when l2_rx_endofpacket is high.
Table 17.   Avalon® Streaming RX MAC Interface Signals All interface signals are clocked by the clk_rxmac clock.

Signal

Direction

Width

Description

clk_rxmac Output 1 Clock for the RX MAC. Generated from the incoming data and is an output from the core (312.5 MHz).
l2_rx_data Output 128

Data output from the MAC. Bit 127 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order. The IP reverses the byte order to meet the requirements of the Ethernet standard.

l2_rx_preamble Output 64

Received preamble data. Available when you select PREAMBLE PASS-THROUGH mode.

Valid when l2_rx_startofpacket is asserted.
l2_rx_valid Output 1 When asserted, indicates that l2_rx_data[127:0] is driving data. When this signal is low, the IP ignores l2_rx_data, l2_rx_startofpacket, l2_rx_endofpacket, l2_rx_empty, and l2_rx_error.
l2_rx_startofpacket Output 1

When asserted, indicates the first byte of a frame.
l2_rx_endofpacket Output 1 When asserted, indicates the last data byte of a frame, before the frame check sequence (FCS). In CRC pass-through mode, it is the last byte of the FCS. The packet can end at any byte position.
l2_rx_empty Output 4 Specifies the number of empty bytes when l2_rx_endofpacket is asserted.

The packet can end at any byte position. The empty bytes are the low-order bytes.
l2_rx_error Output 6

When asserted in the same cycle as l2_rx_endofpacket, indicates the current packet should be treated as an error packet. It is valid when l2_rx_endofpacket is high.

l2_rxstatus_valid Output 1 When asserted, indicates that l2_rxstatus_data is driving valid data.
l2_rxstatus_data[39:0] Output 40

Specifies information about the received frame.

Level Two Title