Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813652
Date 7/22/2024
Public
Document Table of Contents

8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs

Table 33.  Comparison Between Low Latency 40G Ethernet Intel® FPGA IP (alt_e40), Low Latency E-Tile 40G Ethernet Intel® FPGA IP (alt_e40c3), and Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40)

Property

Low Latency 40G Ethernet Intel® FPGA IP

(alt_e40)

Low Latency E-Tile 40G Ethernet Intel® FPGA IP

(alt_e40c3)

Low Latency 40G Ethernet Intel® FPGA IP

(intel_eth_e40)

Transceiver tile support L-Tile, H-Tile E-Tile GTS Transceiver
Device family support

Stratix® 10

Stratix® 10 and Agilex™ 7

Agilex™ 5

Reset

Provides three asynchronous hard reset signals (general, receiver only, and transmitter only) and three soft reset register bits.

Provides three asynchronous hard reset signals (general, receiver only, and transmitter only) and three soft reset register bits.

Provides three asynchronous hard reset signals (general, receiver only, and transmitter only) and three soft reset register bits.
Client interface width

Avalon® streaming interface 128-bit data bus

Avalon® streaming interface 128-bit data bus

Avalon® streaming interface 128-bit data bus

Avalon® streaming transmitter interface readyLatency Avalon® streaming transmitter interface readyLatency configurable at 0 or 3 (parameter). Avalon® streaming transmitter interface readyLatency configurable at 0 or 3 (parameter). Avalon® streaming transmitter interface readyLatency configurable at 0 or 3 (parameter).
Preamble passthrough Available as a configuration option (parameter). When preamble passthrough is turned on, you must provide the preamble on a separate bus, l2_tx_preamble[63:0], and the IP provides the RX preamble on a separate bus, l2_rx_preamble[63:0]. Available as a configuration option (parameter). When preamble passthrough is turned on, you must provide the preamble on a separate bus, l2_tx_preamble[63:0], and the IP provides the RX preamble on a separate bus, l2_rx_preamble[63:0]. Available as a configuration option (parameter). When enabled, In RX preamble pass-through mode, the IP passes the preamble and Start Frame Delimiter (SFD) to the client instead of stripping them out of the Ethernet packet and In TX preamble pass through mode, the client specifies the preamble and provides the SFD to be sent in the Ethernet frame.
Interface to transceiver TX PLL You must instantiate a single TX PLL IP to connect to the single tx_serial_clk input pin of the Low Latency 40G Ethernet Intel® FPGA IP. Not required. Not required.
Statistics counters Available as a configuration option (parameter). Available as a configuration option (parameter). Available as a configuration option (parameter).
Statistics counter increment vectors l2_txstatus_data, l2_txstatus_error, and l2_rxstatus_data signals available on client interface, whether or not statistics registers are enabled. l2_txstatus_data, l2_txstatus_error, and l2_rxstatus_data signals available on client interface, whether or not statistics registers are enabled. l2_txstatus_data, l2_txstatus_error, and l2_rxstatus_data signals available on client interface, whether or not statistics registers are enabled.
40GBASE-KR4 Available as a configuration option. Configurable support for 40GBASE-KR4 or 40GBASE-CR4. Implements the IEEE Backplane Ethernet Standard 802.3-2012. Not supported. Not supported.
Flow control Available as a configuration option (parameter). Available as a configuration option (parameter). Available as a configuration option (parameter).
1588 PTP support Not supported. Not supported. Not supported.
Enable alignment of EOP on FCS word Always turned on. Always turned on. Always turned on.
Minimum average interpacket gap (IPG) Value is 12 bytes. Value is 12 bytes. Value is 12 bytes.
PHY Reference Frequency (MHz)

644.53125

322.265625

156.25 156.25
Synchronous Ethernet (SyncE) Supported Supported Supported