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1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
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6.6. Miscellaneous Status and Debug Signals
These signals are asynchronous.
Signal |
Direction |
Width |
Description |
---|---|---|---|
tx_lanes_stable | Output | 1 | Asserted when all TX lanes are stable and ready to transmit data. |
rx_block_lock | Output | 1 | Asserted when all lanes have identified 66-bit block boundaries in the serial data stream. |
rx_am_lock | Output | 1 | Asserted when all lanes have identified alignment markers in the data stream. |
rx_pcs_ready | Output | 1 | Asserted when the RX lanes are fully aligned and ready to receive data. |
i_system_pll_lock | Input | 1 | Indicates that Sys PLL is locked. |
local_fault_status | Output | 1 | Asserted when the RX MAC detects a local fault. This signal is available only if you turn on Enable link fault generation in the parameter editor. |
remote_fault_status | Output | 1 | Asserted when the RX MAC detects a remote fault. This signal is available only if you turn on Enable link fault generation in the parameter editor. |