Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 7/22/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX MAC Datapath 4.4. RX MAC Datapath 4.5. Flow Control 4.6. Frame Status Checking 4.7. Link Fault Signaling Interface
4.3. TX MAC Datapath x
4.3.1. Preamble Pass-through/Insertion 4.3.2. Padding Bytes Insertion 4.3.3. Deficit Idle Count 4.3.4. TX CRC Insertion/Passthrough 4.3.5. TX Avalon® Streaming Filter 4.3.6. TX PCS 4.3.7. PMA
4.4. RX MAC Datapath x
4.4.1. RX Preamble Pass-through or Removal 4.4.2. RX CRC Checking and Dynamic Option to Forward 4.4.3. Strict SFD/Preamble Checking 4.4.4. RX PCS Functional Description
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
4.6. Frame Status Checking x
4.6.1. Frame Type Checking 4.6.2. Length Checking
5. Clocking and Reset Requirements x
5.1. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. GTS Transceivers Signals 6.4. GTS Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface 6.10. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

7.5. Statistics Counters

The stats module receives vector inputs from the MAC/status vector module and accumulates them into 64-bit Read Only registers. The statistics module provides for the following functions.

Accumulation of Packet Classifications into 64-bit Read Only Registers

The stats module accumulates the following events and packet classification signals into individual 64-bit Read Only registers.

The MAC TX module does not check FCS error for outgoing frames, so it does not report FCS error for outgoing frames. All FCS error related register should be 0. Also, MAC TX does not check outgoing frames for “undersize” error. So, register “Fragments” and “Rnt” should keep value 0.

Statistic counters are implemented with MLAB. After system is powered up in the beginning, the statistic counters have random values. The counter values are not meaningful, and parity error bits could be high. The counter values and parity bits should be cleared before using them.

The address range of these counters in MLAB are from 0x0 to 0x3F and from 0x60 to 0x7F. Some of the addresses in this range are not used. The read access to these unused addresses return random values.

Also, the statistic Counter values are not meaningful if it is read when system is not stable. The read out values should be ignored in this case.

For VLAN or Stacked VLAN frames, if "VLAN detection” is disabled, the VLAN/Stacked VLAN header bytes (4 for VLAN and 8 for Stacked VLAN) are counted into payload bytes.

The following table summarizes the stat counter offsets and their descriptions. The addresses listed give the address of the lower 32 bits of a counter. The upper 32 bits are accessed by adding 1 to the listed address offset.

The TX stats counters have a base address of 0x0800 and the RX counters have a base address of 0x0900.

For example: read address 0x092A to access the RX unicast data packet count.

Table 32.  Statistics and Error Registers
Word Offset Name Typ Default Value Description
0x0 FRAGMENTS RO NA A count of frames which are undersized with a FCS error.
0x2 JABBERS RO NA

A count of oversized frames with an FCS error.
0x4 FCSERR RO NA A count of all packets with an FCS error.
0x6 CRCERR_OKPKT RO NA A count of all packets at least 64 bytes with an FCS error.
0x8 MCAST_DATA_ERR RO NA

A count of multicast data frames with FCS error.
0xa BCAST_DATA_ERR RO NA A count of broadcast data frames with FCS error.
0xc UCAST_DATA_ERR RO NA A count of unicast data frames with FCS error.
0xe MCAST_CTRL_ERR RO NA

A count of multicast control frames with FCS error.
0x10 BCAST_CTRL_ERR RO NA A count of broadcast control frames with FCS error.
0x12 UCAST_CTRL_ERR RO NA A count of unicast control frames with FCS error.
0x14 PAUSE_ERR RO NA A count of pause control frames with an FCS error.
0x16 64B RO NA This counts all packets with length equal to 64 Bytes.
0x18 65to127B RO NA This counts all packets with length from 65 Bytes up-to 127 Bytes.
0x1a 128to255B RO NA This counts all packets with length from 128 Bytes up-to 255 Bytes.
0x1c 256to511B RO NA This counts all packets with length from 256 Bytes up-to 511 Bytes.
0x1e 512to1023B RO NA This counts all packets with length 512 Bytes to 1023 Bytes.
0x20 1024to1518B RO NA This counts all packets with length 1024 Bytes to 1518 Bytes.
0x22 1519toMAXB RO NA This counts all packets with length from 1519 to size specified in the size specified in the max packet size register.
0x24 OVERSIZE RO NA This counts all packets with length more than the size specified in the max frame size register.
0x26 MCAST_DATA_OK RO NA A count of multicast data frames without an FCS error.
0x28 BCAST_DATA_OK RO NA A count of broadcast data frames without an FCS error.
0x2a UCAST_DATA_OK RO NA A count of unicast data frames without an FCS error.
0x2c MCAST_CTRL_OK RO NA A count of multicast control frames without an FCS error.
0x23 BCAST_CTRL_OK RO NA A count of broadcast control frames without an FCS error.
0x30 UCAST_CTRL_OK RO NA A count of unicast control frames without an FCS error.
0x32 PAUSE RO NA A count of pause control frames without an FCS error.
0x34 RNT RO NA This counts all packets with length less than64 Bytes.
0x45 CNTR_CONFIG RO NA

This is a stats counter control register.

  • Set bit 0 to clear the stats counters. This is self-clearing.
  • Set bit 1 to clear parity errors in counter memory. This is self-clearing.
  • Set bit 2 to assert a shadow request.
0x46 CNTR_STATUS RO NA

This is a status register.

  • Bit 0 indicates a counter memory parity error.
  • Bit 1 indicates that the shadow request has been granted.
0x60 Payload OctetsOK RO NA This is a 64-bits register. It represents the cumulative value of Payload Octets for good frames Transmitted/Received.
0x62 Frame OctetsOK RO NA This is a 64-bits register. It represents the cumulative value of Frame Octets for good frames Transmitted/Received.
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