ID
813652
Date
7/22/2024
Public
Visible to Intel only — GUID: nmj1703832673514
Ixiasoft
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
Visible to Intel only — GUID: nmj1703832673514
Ixiasoft
1. About the Low Latency 40G Ethernet Intel® FPGA IP
Updated for: |
---|
Intel® Quartus® Prime Design Suite 24.2 |
IP Version 3.0.0 |
The Low Latency 40G Ethernet Intel® FPGA IP for Agilex™ 5 devices is an integrated MAC and PHY solution with GTS transceiver conforming to the IEEE 802.3 Standard. The MAC interfaces with its client via (128-bit) Avalon® streaming interface for data-path and a 32-bit Avalon® memory-mapped interface for control and status path. This IP supports Standard XLAUI interfaces on network interface and it does not support the KR4, backplane feature.
Figure 1. Low Latency 40G Ethernet Intel® FPGA IP Block DiagramMain blocks, internal connections, and external block requirements.
Note: Device support for Agilex™ 5 D-Series FPGAs and SoCs in the Quartus® Prime Pro Edition software version 24.2 is restricted. To enable D-Series device support in your instance of the Quartus® Prime Pro Edition software, contact your regional Altera sales representative.