Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813652
Date 7/22/2024
Public
Document Table of Contents

4.4.2. RX CRC Checking and Dynamic Option to Forward

The Ethernet MAC checks the incoming CRC-32 for any errors and generate a single cycle CRC error signal at end-of-packet when an error is detected. The CRC checking takes several cycles, and the packet frame is delayed to align the CRC output with the end of the frame. In the default mode, the RX MAC strips off the CRC bytes before forwarding the packet to the MAC client.