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1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
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1.3. Resource Utilization
Resource utilization changes depending on the parameter settings you specify in the Low Latency 40G Ethernet IP parameter editor. For example, if you turn on statistics counters in the Low Latency 40G Ethernet IP parameter editor, the IP requires additional resources to implement the additional functionality.
IP Variation | A | B | C | E | F |
---|---|---|---|---|---|
Parameter | |||||
Ready latency | 0 | 0 | 3 | 3 | 3 |
Enable TX CRC insertion | — | On | On | On | On |
Enable link fault generation | — | — | On | — | — |
Enable preamble passthrough | — | — | On | — | — |
Enable MAC stats counters | — | On | On | On | On |
Enable Strict SFD Check | — | — | On | — | On |
IP Variation |
ALMs |
Dedicated Logic Registers |
Memory M20K |
---|---|---|---|
A | 9959 | 19260 | 4 |
B | 12962 | 25451 | 4 |
C | 13846 | 27592 | 4 |
E | 13147 | 25763 | 4 |
F | 13157 | 25936 | 4 |
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