Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813652
Date 7/22/2024
Public

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4.4. RX MAC Datapath

This section describes the RX MAC and PCS functions.

Functional Description

A high-level diagram for RX MAC is shown in the following figure.
Figure 10. RX MAC Datapath