Visible to Intel only — GUID: mtv1704169949018
Ixiasoft
Visible to Intel only — GUID: mtv1704169949018
Ixiasoft
6.9. Flow Control Interface
Signal Name |
Direction |
Width |
Description |
---|---|---|---|
pause_insert_tx0 |
Input | QN |
These signals are available only if Pause or PFC flow control support is synthesized. Indicates the MAC whether a XON or XOFF Pause or PFC flow control frame should be sent.
The request for XON/XOFF flow control frame transmission can be done in either 1 or 2-bit request mode (see pause_insert_tx1). 1-bit mode request model:
The following encoding is defined:
2-bit mode request model: Represents the lower bit. Only takes effect when the CSR of 2-bit Flow Control Request mode selects "Signal". The following encoding is defined:
|
pause_insert_tx1 | Input | QN | Used in conjunction with pause_insert_tx0 to form a 2-bit request for XON/XOFF flow control frame transmission. This represents the upper bit of the 2-bit control. |
pause_receive_rx | Output | QN | Asserted to indicate an RX pause signal match. The IP asserts bit [n] of this signal when it receives a pause request with an address match, to signal the TX MAC to throttle its transmissions from priority queue [n] on the Ethernet link. |