Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813652
Date 7/22/2024
Public
Document Table of Contents

6.10. GTS Reset Sequencer Intel® FPGA IP

Table 25.   GTS Reset Sequencer Interface Signals
Port Name Port Width Port Direction Description
o_src_rs_req 4 Output Request from IP to GTS Reset Sequencer Intel® FPGA IP for reset exit.
i_src_rs_grant 4 Input Ack from GTS Reset Sequencer Intel® FPGA IP to Base IP for reset grant for SRC CH.