Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813652
Date 7/22/2024
Public
Document Table of Contents

1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support

Table 1.   Intel® FPGA IP Device Support Levels

Device Support Level

Definition

Advance

The IP is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (datapath width, burst depth, I/O standards tradeoffs).

Preliminary

The IP is verified with preliminary timing models for this device family. The IP meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.

Final

The IP is verified with final timing models for this device family. The IP meets all functional and timing requirements for the device family and can be used in production designs.

Table 2.   Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) Device Family SupportShows the level of support offered by the Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) for each Intel FPGA device family.
Device Family Support
Agilex™ 5 Preliminary

Other device families

No support