Visible to Intel only — GUID: bxj1704169741311
Ixiasoft
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
Visible to Intel only — GUID: bxj1704169741311
Ixiasoft
6.5. Avalon® Memory-Mapped Management Interface
Signal |
Direction |
Width |
Description |
---|---|---|---|
clk_status | Input | 1 | The clock that drives the control and status registers. |
status_addr | Input | 16 | Register address. |
status_read | Input | 1 | When asserted, specifies a read request. |
status_write | Input | 1 | When asserted, specifies a write request. |
status_readdata | Output | 32 | Drives read data. |
status_readdata_valid | Output | 1 | Register read data valid. |
status_writedata | Input | 32 | Drives the write data. |
status_waitrequest | Output | 1 | Wait request. Indicates that the device is not ready to complete the transaction. The status_waitrequest signal is only used for read transactions. Refer to the Avalon® Interface Specifications for more details. |
Related Information