Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813652
Date 7/22/2024
Public
Document Table of Contents

6.1. TX MAC Interface to User Logic

The Ready Latency could be configured to 0 or 3 for easier timing closure. The user interface for the TX MAC is an Avalon® streaming interface. The data is 128 bits wide, consisting of 2 words of 64 bits each. Packets with SOP and EOP in the same word are ignored; the minimum supported packet size is 9 bytes. If l2_tx_startofpacket is set, it implies that the MSB of l2_tx_data has the start of packet. The l2_tx_empty vector indicates how many bytes in the last transfer are not valid; it only has meaning when l2_tx_endofpacket is asserted. Once a start of packet is seen on the bus, all data until l2_tx_endofpacket is assumed to be part of the packet. The packet ends with l2_tx_endofpacket.
Table 16.   Avalon® Streaming TX MAC Interface SignalsAll interface signals are clocked by the clk_txmac clock. The value you specify for Ready latency in the Low Latency 40G Ethernet IP parameter editor for Agilex™ 5 devices is the Avalon® streaming interface readyLatency value on this interface.

Signal

Direction

Width

Description

clk_txmac Output 1

The derived clock from the input clk_ref_p.

l2_tx_data Input 128

Data input to MAC. Bit 127 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order.

l2_tx_preamble Input 64

User preamble data. Available when you turn on Enable preamble passthrough mode.

User logic drives the custom preamble data when l2_tx_startofpacket is asserted.

The l2_tx_preamble [63:56] has to be 8’hfb.

l2_tx_valid Input 1 When asserted, indicates valid data.
l2_tx_startofpacket Input 1 When asserted, indicates the first byte of a frame.
l2_tx_endofpacket Input 1 When asserted, indicates the end of a packet.
l2_tx_empty Input 4 Specifies the number of empty bytes when l2_tx_endofpacket is asserted.
l2_tx_ready Output 1 When asserted, indicates that the MAC can accept the data. The data is processed only when l2_tx_ready is asserted.
l2_tx_error Input 1 A high on this signal aligned with a valid EOP indicates that the current packet needs to be treated as error packet
l2_txstatus_valid Output 1 When asserted, indicates that l2_txstatus_data is driving valid data.
l2_txstatus_data Output 40

Specifies information about the transmit frame.

l2_txstatus_error Output 7

Specifies the error type in the transmit frame.

Figure 15.  Client to MAC Avalon® Streaming Interface l2_tx_data reception order is highest byte to lowest byte. The first byte of the destination address is on l2_tx_data[127:120] , 0xabe4233 . . . in this timing diagram. The ready latency is 0 in this example.