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1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
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6.7. Reset Signals
The reset controller has soft reset signals, which are asserted by the CSR, and three asynchronous resets, which are asserted externally.
Signal |
Clock Domain |
Description |
---|---|---|
tx_rst_n | Asynchronous | Resets the TX PCS and MAC. Active low. |
tx_rst_ack_n | Asynchronous | Resets the ACK TX and MAC. Active low. |
rx_rst_n | Asynchronous | Resets the RX PCS and MAC. Active low. |
rx_rst_ack_n | Asynchronous | Resets the ACK RX PCS and MAC. Active low. |
csr_rst_n | Asynchronous | Resets the full IP. Includes transmit and receive MACs, PCS, adapters, transceivers, as well as configuration and status registers. Active low. |
csr_rst_ack_n | Asynchronous | Resets ACK for CSR reset. Active low. |
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