Visible to Intel only — GUID: koz1707462805639
Ixiasoft
Visible to Intel only — GUID: koz1707462805639
Ixiasoft
4.3.6. TX PCS
The TX PCS has four main components:
Block Encoder
The block encoder takes the 64-bit data blocks and 8-bit control blocks and encodes them into 66 bit encoded blocks. The TX PCS encodes two blocks per clock cycle.
Scrambler
The TX PCS scrambler takes two encoded blocks per clock cycles and scrambles them and produces two scrambled data blocks per clock cycle.
Alignment Marker Insertion
The alignment marker insertion blocks are used to insert an alignment marker on each virtual lane every 16,384 data blocks. The generation of the alignment markers.
Block Distributor
The block distributor takes the scrambled data blocks and alignment marker and distributes them round robin to the four virtual lanes.
TX PCS Interface
Name | I/O | Width | Description |
---|---|---|---|
Clk | Input | 1 | Main register clock. Runs at 312.5 MHz. |
din_d | Input | 128 | MII data input. Takes two data blocks per cycle. |
din_c | Input | 16 | MII control input. Takes two control blocks per cycle. |
din_am | Input | 1 | Alignment marker insertion indicator. When asserted, the TX PCS ignores the data presented on the MII port and insert alignment markers instead. This should be asserted for two cycles in a row to insert all four alignment markers. |
dout | Output | 264 | Scrambled data and alignment marker output. This interface presents all four physical lane data blocks at once. |
Valid | Output | 1 | Indicates that the data presented on dout is valid. This is likely asserted every other PCS clk cycle and used to drive the PMA FIFO write signal. |
TX PCS-PMA Interface
In the Low Latency 40G Ethernet design, the interface between the PCS and the TX PMA is through PMA direct PHY IP and 66 bits per virtual lane giving a total parallel width of 264 bits.
In this design the GTS PMA input data width is 80 bits. The 66 bits from PCS is converted into the respective 80-bit and forwarded to the GTS PMA as TX parallel data.