Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813652
Date 7/22/2024
Public
Document Table of Contents

3.5. Generated File Structure

The Quartus® Prime Pro Edition software generates the following output files for Low Latency 40G Ethernet Intel® FPGA IP for Agilex™ 5 devices.
Figure 5. IP Generated Files
Table 10.  IP Generated Files

File Name

Description

<your_ip>.ip

The Platform Designer system or top-level IP variation file. <your_ip> is the name that you give your IP variation.

<your_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.

This IP does not support VHDL. However, the Quartus® Prime Pro Edition generates this file.

<your_ip>.html

A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.

<your_ip>_generation.rpt IP or Platform Designer generation log file. A summary of the messages during IP generation.
<your_ip>.qgsimc Lists simulation parameters to support incremental regeneration.
<your_ip>.qgsynthc Lists synthesis parameters to support incremental regeneration.
<your_ip>.qip

Contains all the required information about the IP component to integrate and compile the IP component in the Quartus® Prime Pro Edition software.

<your_ip>.csv Contains information about the upgrade status of the IP component.

<your_ip>.bsf

A Block Symbol File (.bsf) representation of the IP variation for use in Quartus® Prime Block Diagram Files (.bdf).

<your_ip>.spd

Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<your_ip>_bb.v You can use the Verilog black-box (_bb.v) file as an empty module declaration for use as a black box.
<your_ip>_inst.v or _inst.vhd HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation.

This IP does not support VHDL. However, the Quartus® Prime Pro Edition generates the _inst.vhd file.

<your_ip>.v HDL files that instantiate each submodule or child IP for synthesis or simulation.
mentor/

Contains a ModelSim* script msim_setup.tcl to set up and run a simulation.

aldec/

Contains a Riviera-PRO* script rivierapro_setup.tcl to setup and run a simulation.

This IP does not support simulation with the Riviera-PRO* simulator. However, the Quartus® Prime Pro Edition software generates this directory.

synopsys/vcs/

synopsys/vcsmx/

Contains a shell script vcs_setup.sh to set up and run a VCS* simulation.

Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS* MX simulation.

cadence/

Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSim simulation.

submodules/ Contains HDL files for the IP submodule.
<child IPs>/ For each generated child IP directory, Platform Designer generates synth/ and sim/ sub-directories.
IPUpgradeLog.xml The generated file when IP are upgraded from the previous version.

For information about the file structure of the design example, refer to the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs .