Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813652
Date 7/22/2024
Public
Document Table of Contents

3.7. Testbench

Altera® provides a compilation-only example design and a testbench with most variations of the Low Latency 40G Ethernet Intel® FPGA IP for Agilex™ 5 devices.

To generate the testbench, you must first set the parameter values for the IP variation you intend to generate. If you do not set the parameter values identically, the testbench you generate might not exercise the IP variation you generate. If your IP variation does not meet the criteria for a testbench, the generation process does not create a testbench.