7.4. Pause/PFC Flow Control
Addr | Bit | Name | Description | Reset | Access |
---|---|---|---|---|---|
0x600 | 31:0 | TX Flow Control Revision ID | Provide 32-bit TX Flow Control Revision ID. | 0x0916_2016 | RO |
0x601 | 31:0 | TX Flow Control Scratch Pad | Provide 32-bit TX Flow Control Scratch Pad Value. | 0 | RW |
0x602 | 31:0 | TX Flow Control IP Core Variant 0 | First 4 characters of IP variation identifier ASCII string, "40GE FCTx CSR" | 0x35304745 | RO |
0x603 | 31:0 | TX Flow Control IP Core Variant 1 | Next 4 characters of IP variation identifier ASCII string. | 0x4643_5478 | RO |
0x604 | 31:0 | TX Flow Control IP Core Variant 2 | Final 4 characters of IP variation identifier ASCII string | 0x0043_5352 | RO |
0x605 | 7:0 | TX Flow Control Enable |
Enables the IP to generate XON and XOFF Pause/PFC flow control frames to the remote partner. The following encodings are defined:
You can change this field dynamically. |
0xff | RW |
31:8 | Reserved | Reserved. | 0 | RO | |
0x606 | 7:0 | TX Flow Control CSR XON/XOFF Request 0 | XON/XOF flow control frame request bit 0. Interpretation depends on whether the IP is in 1-bit FC request mode or in 2-bit FC request mode. This register affects a flow control queue only if the corresponding bit of the TX Flow Control Enable register has the value of 1. The following encodings are defined for 1-bit mode.
The following encodings are defined for 2-bit mode.
You can modify the value of this field dynamically. |
0 | RW |
15:8 | Reserved | Reserved | 0 | RO | |
23:16 | TX Flow Control CSR XON/XOFF Request 1 | In conjunction with Flow Control XON/XOFF Request 0 specifies a 2-bit request for XON/XOFF flow control frame transmission. This bit is the upper bit of the 2-bit control field. You can change the value of this field dynamically. |
0 | RW | |
31:24 | Reserved | Reserved. | 0 | RO | |
0x607 | 31:0 | Reserved | Reserved. | 0 | RO |
0x608 | 15:0 | Reserved | Reserved. | 0 | RO |
31:16 | Reserved | Reserved. | 0 | RO | |
0x609 | 15:0 | Reserved | Reserved. | 0 | RO |
31:16 | Reserved | Reserved. | 0 | RO | |
0x60A | 0 | TX Pause Enable 1-bit |
Determines whether receiving a valid Pause frame stops TX user data transmission.
You cannot change the value of this field dynamically. |
0 | RW |
31:1 | Reserved | Reserved. | 0 | RO | |
0x60B | 31:0 | Reserved | Reserved. | 0 | RO |
0x60C | 31:0 | Reserved | Reserved. | 0 | RO |
0x60D | 31:0 | TX Flow Control Destination Address Lower | Specifies the 48-bit Destination Address of the flow control frame. Contains the 32 LSB of the address field. You cannot modify the value of this field dynamically. |
0xC2000001 | RW |
0x60E | 15:0 | TX Flow Control Destination Address Upper | Specifies the 48-bit Destination Address of flow control frame. Contains the 16 MSB of the address field. You cannot modify the value of this field dynamically. |
0x0180 | RW |
31:16 | Reserved. | 0 | RO | ||
0x60F | 31:0 | TX Flow Control Source Address Lower | Specifies the 48-bit Source Address of flow control frame. Contains the 32 LSB of the address field. |
0xCBFC5ADD | RW |
0x610 | 15:0 | TX Flow Control Source Address Upper | Specifies the 48-bit Source Address of flow control frame. Contains the 16 MSB of the address field. You cannot modify the value of this field dynamically. |
0xE100 | RW |
31:16 | Reserved | Reserved. | 0 | RO | |
0x620 + (QN), where QN = 0 to 7 | 15:0 | TX Flow Control Quanta 16-bit per FCQN |
Specifies the pause quanta of Pause/PFC flow control frames to be sent to remote partner. You cannot modify the value of this field dynamically. |
0xFFFF | RW |
31:16 | Reserved | Reserved. | 0 | RO | |
0x628 + (QN), where QN = 0 to 7 | 15:0 | TX Flow Control Signal XOFF Request Hold Quanta 16-bit per FCQN |
Specifies the separation between 2 consecutive XOFF flow control frames. You cannot modify the value of this field dynamically. |
0xFFFF | RW |
31:16 | Reserved | Reserved. | 0 | RO | |
0x640 | 0 | TX Flow Control Select 1-bit |
Specifies whether the TX hardware generates Pause or PFC frames. Affects only PFC Queue 0. Usage example: You can synthesize a single PFC queue and use it for both Pause and PFC purpose.
You cannot modify the value of this field dynamically. |
1 | RW |
31:1 | Reserved. | Reserved. | 0 | RO | |
0x641 | FCQN-1:0 | TX 2-bit Flow Control Request Mode 1-bit per FCQN |
Determines whether the TX Flow Control CSR XON/XOFF Request register or the pause_insert_tx0 and pause_insert_tx1 signals control XON/XOFF mode in 2-bit control mode.
You cannot modify the value of this field dynamically. |
0 | RW |
16 | TX Flow Control Request Mode 1 bit for all FCQN |
Determines whether the IP is in TX flow control 1-bit mode or 2-bit mode.
|
0 | RW | |
31:17 | Reserved | Reserved. | 0 | RO |
Addr | Bit | Name | Description | Reset | Access |
---|---|---|---|---|---|
0x700 | 31:0 | RX Flow Control Revision ID | Provide 32-bit RX Flow Control Revision ID. | 0x09162016 | RO |
0x701 | 31:0 | RX Flow Control Scratch Pad | Provide 32-bit RX Flow Control Scratch Pad Value. | 0 | RW |
0x702 | 31:0 | RX Flow Control IP Core Variant 0 | First 4 characters of IP variation identifier ASCII string, "40GE FCTx CSR". |
0x35304745 | RO |
0x703 | 31:0 | RX Flow Control IP Core Variant 1 | Next 4 characters of IP variation identifier ASCII string. | 0x4643_5278 | RO |
0x704 | 31:0 | RX Flow Control IP Core Variant 2 | Final 4 characters of IP variation identifier ASCII string. | 0x0043_5352 | RO |
0x705 | 7:0 | RX PFC Enable |
Determines whether receiving a valid PFC frame causes the PFC duration user interface to indicate a valid pause quanta duration to the user logic. 0: Disable 1: Enable You cannot modify the value of this field dynamically. |
RW | |
31:8 | Reserved | Reserved. | 0 | RO | |
0x706 | 0 | Reserved | Reserved. | 0 | RO |
7:1 | Reserved | Reserved. | 0 | RO | |
8 | Reserved | Reserved. | 0 | RO | |
31:9 | Reserved | Reserved. | 0 | RO | |
0x707 | 31:0 | RX Flow Control Destination Address Lower | Specifies the 48-bit Destination Address of the flow control frame. Contains the 32 LSB of the address field. You cannot modify the value of this field dynamically. Incoming pause frame DA need to match with this address to have flow control working. |
0xC2000001 | RW |
0x708 | 15:0 | RX Flow Control Destination Address Upper | Specifies the 48-bit Destination Address of flow control frame. Contains the 16 MSB of the address field. You cannot modify the value of this field dynamically. Incoming pause frame DA need to match with this address to have flow control working. |
0x0180 | RW |
31:16 | Reserved | Reserved, | 0 | RO |