Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813652
Date 7/22/2024
Public
Document Table of Contents

6.8. Clocks

Table 23.  Clock Signals
Signal Name Direction Width Nominal Frequency (MHz) Description
clk_txmac Output 1 312.5 Clock for TX section.
clk_rxmac Output 1 312.5 Clock for RX section.
clk_ref_p Input 1 156.25 This clocks the CDR in the receive direction of the transceivers – differential clk.
i_system_pll_clk Input 1 156.25 Syspllclk from sys_clk_IP.
clk_status Input 1 100 to 125 Avalon® memory-mapped interface clock.
reconfig_clk Input 1 100 to 125 Transceiver reconfiguration clock.
i_pma_cu_clk Input 1 250

Input from GTS Reset Sequencer Intel® FPGA IP to Low Latency 40G Ethernet Intel® FPGA IP.

It is one per QUAD feeding the FLUX uC in the transceiver.