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1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
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6.8. Clocks
Signal Name | Direction | Width | Nominal Frequency (MHz) | Description |
---|---|---|---|---|
clk_txmac | Output | 1 | 312.5 | Clock for TX section. |
clk_rxmac | Output | 1 | 312.5 | Clock for RX section. |
clk_ref_p | Input | 1 | 156.25 | This clocks the CDR in the receive direction of the transceivers – differential clk. |
i_system_pll_clk | Input | 1 | 156.25 | Syspllclk from sys_clk_IP. |
clk_status | Input | 1 | 100 to 125 | Avalon® memory-mapped interface clock. |
reconfig_clk | Input | 1 | 100 to 125 | Transceiver reconfiguration clock. |
i_pma_cu_clk | Input | 1 | 250 | Input from GTS Reset Sequencer Intel® FPGA IP to Low Latency 40G Ethernet Intel® FPGA IP. It is one per QUAD feeding the FLUX uC in the transceiver. |