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1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
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3.8. Compiling the Full Design and Programming the FPGA
You can use the Start Compilation command on the Processing menu in the Quartus® Prime software to compile your design. After successfully compiling your design, program the targeted Intel® FPGA with the Programmer and verify the design in hardware.
Note: The Low Latency 40G Ethernet Intel® FPGA IP design example synthesis directories for Agilex™ 5 devices include Synopsys Constraint (.sdc) files that you can copy and modify for your own design.