Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813652
Date 7/22/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX MAC Datapath 4.4. RX MAC Datapath 4.5. Flow Control 4.6. Frame Status Checking 4.7. Link Fault Signaling Interface
4.3. TX MAC Datapath x
4.3.1. Preamble Pass-through/Insertion 4.3.2. Padding Bytes Insertion 4.3.3. Deficit Idle Count 4.3.4. TX CRC Insertion/Passthrough 4.3.5. TX Avalon® Streaming Filter 4.3.6. TX PCS 4.3.7. PMA
4.4. RX MAC Datapath x
4.4.1. RX Preamble Pass-through or Removal 4.4.2. RX CRC Checking and Dynamic Option to Forward 4.4.3. Strict SFD/Preamble Checking 4.4.4. RX PCS Functional Description
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
4.6. Frame Status Checking x
4.6.1. Frame Type Checking 4.6.2. Length Checking
5. Clocking and Reset Requirements x
5.1. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. GTS Transceivers Signals 6.4. GTS Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface 6.10. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features

The Low Latency 40G Ethernet Intel® FPGA IP supports the following features:

  • Parameterizable through the IP Catalog available with the Quartus® Prime Pro Edition software.
  • Designed to the IEEE 802.3 High Speed Ethernet Standard available on the IEEE website (www.ieee.org).
  • Soft PCS logic that interfaces seamlessly to Intel® FPGA with 10.3125 gigabits per second (Gbps) serial transceivers.
  • Standard XLAUI external interface consisting of FPGA hard serial transceiver lanes operating at 10.3125 Gbps. IP supports the automatic reordering of Rx PCS virtual lanes. The link works even if the XCVR lanes are swapped on the PCB. However, the IP top level serial interface wire tx/rx_serial[n] must be connected to the PMA GTS CH-n.
  • Supports Synchronous Ethernet (SyncE) by providing an optional CDR recovered clock output signal to the device fabric.
  • Avalon® memory-mapped management interface to access the IP control and status registers.
  • Avalon® streaming interface provides data path interface with 128-bit data width that connects to client logic with the start of frame in the most significant byte (MSB).
  • Support for jumbo packets, defined as packets greater than 1500 bytes. The width of the MAX packet size configuration register for the Tx and Rx is 16-bit. If the packet length is more than the configured size, then IP indicates through oversized error status but the IP does not truncate the packet to the max size, the packet is not accepted and transmitted even after the MAX size.
  • Receive (RX) CRC removal and pass-through control.
  • Optional transmit (TX) CRC generation and insertion.
  • RX CRC checking and error reporting.
  • RX and TX preamble pass-through option for applications that require proprietary user management information transfer.
  • Optional RX strict SFD checking per IEEE specification.
  • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length.
  • Received control frame type indication.
  • Unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard.
  • Hardware and software reset control.
  • MAC provides RX cut-through frame processing, no RX store-and-forward capability.
  • Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average.
  • Optional fault signaling detects and reports local fault and generates remote fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
  • Programmable ready latency of 0 or 3 clock cycles for Avalon® streaming TX interface.
  • Optional statistics counters.

For a detailed specification of the Ethernet protocol refer to the IEEE 802.3 Ethernet Standard.

Related Information
Level Two Title