PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

6.2.1. Top Level Interfaces

The PHY Lite for Parallel Interfaces Intel® FPGA IP consists of the following ports:

  • Clocks and reset
  • Core data and control (divided into input and output paths)
  • I/O (divided into input and output paths)
  • Avalon® memory-mapped interface configuration bus (available only when Dynamic Reconfiguration feature is enabled)
Figure 144. Top-Level InterfaceThis figure shows the top-level diagram of the PHY Lite for Parallel Interfaces Intel® FPGA IP interface.