PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

5.5.3. Reset

You can source the reset to the PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 devices from an external pin or from the core. If you source the reset from an external pin, you must configure the I/O standard of the reset signal in the .qsf file with the following command:
set_location_asignment <PIN_NUMBER> -to <signal_name>