PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

6.3.1.1. Read Latency

Table 132.  Minimum Read Latency This table shows the minimum read latency value supported by PHY Lite for Parallel Interfaces Intel® FPGA IP based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate VCO Multiplier Factor Read Latency (External Memory Clock Cycle)
Full rate 1 4
2 4
4 3
8 3
Half rate 1 5
2 5
4 4
8 4
Quarter rate 1 7
2 7
4 7
8 7