PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

3.2.1.2. Output Path

The simplified output path consists of pipeline registers, TX FIFO, shift register, and phase shift blocks. The following figure shows strobe and data coming from the core, together with the related enable signals, go through the pipeline stages before the TX FIFO.
Figure 38. Simplified Output PathThis figure shows the simplified output path for the PHY Lite for Parallel Interfaces Intel® FPGA IP.
Table 36.  Components in Simplified Output Path
Component Description
Pipeline Registers Represent pipeline stages in the output path.
TX FIFO Stores the data to be transmitted out.
Shift Register Delays the enable signal at the read side of the TX FIFO at VCO cycle increment.
Phase Shift Delays TX data and strobe at 1/128 of a VCO cycle increments.

There are two types of delays in the output path, namely inherent latency and output delay, TxDqDelay.

Table 37.  Types of Delay in Output Path
Delay Type Description
Inherent latency Static

Captured in the pipeline stages from the assertion of the output enable in the core (group_<n>_oe_from_core[]) until the data go into TX FIFO.

The parameter Additional Write Latency in the IP Parameter Editor is added to the inherent latency.

TxDqDelay delay (output delay) Dynamic You can configure this 11-bit wide register in the control registers. The TxDqDelay register consists of two parts, as described in the next table. The integer part of the delay uses a shift register to delay the enable signal that goes to the read side of TX FIFO.
Table 38.  Output Path Reconfigurable Delays DescriptionThis table describes the reconfigurable output path delay.
Feature Description Min Max
TxDqDelay

[10:7]

Integer number of VCO clock cycles. The integer portion of the delay is accomplished using a shift register to delay the enable signal that goes to the read side of the TX FIFO. 0 15
TxDqDelay

[6:0]

Additional phase shift measured in 1/128 of VCO clock period. 0 127
Figure 39. Output OperationThis figure shows the output operation for the PHY Lite for Parallel Interfaces Intel® FPGA IP.

The preceding figure shows an example of TX data transfer in QR DDR. The data_from_core for each pin is 8 bits wide. To enable one extra preamble cycle before the data starts, wait for strobe_out_en to transition from 0 to h8 in one core clock cycle before the oe_from_core signal, as shown in the figure. Setting Output strobe phase to 90 degrees causes the PHY Lite IP to send the data center aligned.