PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

5.4.2. On-Chip Termination (OCT)

PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 devices provides valid OCT settings for each group (refer to the I/O Standards topic). These settings are written to the .qip of the instance during generation. If you select an I/O standard that supports OCT in the General tab, you can use the OCT blocks provided in Stratix® 10 devices.

You can instantiate the OCT block in one of two ways:

  • Using RZQ_GROUP assignment in the assignment editor, or
  • Manual insertion of OCT block