PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

6.7.1. Implementation using the PHY Lite for Parallel Interfaces Intel® FPGA IP

You can configure the PHY Lite for Parallel Interfaces Intel® FPGA IP to support multiple groups (maximum 48 I/O pins each).

The following lists the possible implementations:

  • Instantiates one PHY Lite for Parallel Interfaces Intel® FPGA IP with two groups
    • Bidirectional type for DQ and DQS signals
    • Output type for Addr/Cmd signals
Note: Each group in the PHY Lite for Parallel Interfaces Intel® FPGA IP can have 48 I/Os, and the IP supports up to 18 groups.
Figure 177.  General Tab Settings


Figure 178.  Group 0 Settings (Bidirectional Type for DQ and DQS)


Figure 179.  Group 1 Settings (Output Type for Addr/Cmd)