PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

3.2.3. I/O Timing

Intel recommends that you design your system for the worst case losses for the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 devices.
Table 47.  Worst Case Losses for PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 DevicesIn the following table, assume that the PHY Lite for Parallel Interfaces IP instance communicates with another PHY Lite for Parallel Interfaces IP instance.
Data Flow Direction Applies to PHY Lite for Parallel Interfaces Intel® FPGA IP Mode Worst Case Losses
Driving (PHY Lite for Parallel Interfaces Intel® FPGA IP is driving the I/Os) Output or bi-directional 40% UI
Receiving (PHY Lite for Parallel Interfaces Intel® FPGA IP is sampling the I/Os) Input or bi-directional 35% UI
Minimum Receiving Eye Height (PHY Lite for Parallel Interfaces Intel® FPGA IP is sampling the I/Os) Input or bi-directional 100 mV