PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

4.4. I/O Standards

The PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 devices allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups. For Agilex™ 7 F-Series and I-Series devices, the PHY Lite for Parallel Interfaces Intel® FPGA IP instances in the same I/O bank should have the same IO standard.

Table 74.  I/O Standards and Termination Values for Agilex™ 7 F-Series and I-Series Devices
I/O Standard Valid Input Terminations (Ω) Valid Output Terminations (Ω) RZQ (Ω)
SSTL-12 50, 60 34, 40 240
1.2-V POD 50, 60 34, 40 240