Visible to Intel only — GUID: kly1441845719889
Ixiasoft
Visible to Intel only — GUID: kly1441845719889
Ixiasoft
6.6.1. Generating the Design Example
You can generate a design example by clicking Generating Example Design in the IP Parameter Editor.
The software generates a user defined directory in which the design example files reside.
- Variant without dynamic reconfiguration design example
- Variant with dynamic reconfiguration design example
Design Example Variant | Design Files | Description | |
---|---|---|---|
Dynamic Reconfiguration | OFF | ed_synth.qsys (synthesis only) | Consists of configurable PHY Lite for Parallel Interfaces Intel® FPGA IP instance. |
ed_sim.qsys (simulation only) | Consists of sim_ctrl, agent, addr/cmd and PHY Lite for Parallel Interfaces Intel® FPGA IP instances. Perform read and write transaction verification. |
||
ON | ed_synth.qsys (synthesis only) | Consists of IOAUX and PHY Lite for Parallel Interfaces Intel® FPGA IP instances. You need to instantiate NIOS and AVL_Controller manually or create user logic to perform address translation. |
|
phylite_debug_kit.qsys (synthesis only) | Consists of NIOS, AVL_Controller, API functions, IOAUX and PHY Lite for Parallel Interfaces Intel® FPGA IP instances. A recommended example design to perform dynamic reconfiguration. This design example does not support simulation. |
||
ed_sim.qsys (simulation only) | Consists of sim_ctrl, agent, addr/cmd, cfg_ctrl, avl_ctrl and PHY Lite for Parallel Interfaces Intel® FPGA IP core instances. This design example demonstrates dynamic reconfiguration and uses FSM to perform calibration. |